OBJECTIVE:
A position as a Process Technician in the Solar, LED or Semiconductor Microelectronics Industries, utilizing extensive experience on AMAT CVD/Etch systems, Scanning Electron Microscopes (SEM, FESEM), diffusion furnaces, reactive ion etchers, sputters, evaporators and standard semiconductor metrology/test equipment.
BACKGROUND:
Decisive, action-oriented and results-focused business professional, offering over ••••• years of high-tech experience in the Solar, LED and Semiconductor Microelectronics Industries. Experienced with high quality environments, lo-tech R&D environments, troubleshooting and process improvements, generating data as part of a research and development team. Accurate and repeatable work ethic, with special attention to details and process trending.
EMPLOYMENT SUMMARY:
•••••/••••• –•••••/•••••
R&D TECHNICIAN
Philips Lumileds
San Jose, CA
-Work with engineers to optimize LED output
-Prepare sapphire wafer lots to be processed through the wafer fab.
-Process wafers through various semiconductor equipment (spin coaters, aligners, developers, etchers, CVD reactors, sputters, furnaces, chemical baths, etc.) used to produce LEDs.
-Evaluate and optimize new equipment.
-Use testing equipment to evaluate the light output of experimental runs.
-Use scanning electron microscopes (SEM) to analyze and optimize resist profiles (pre- and post-etch), etch profiles and surface morphology of different films.
-Optimize processes for new, experimental resists in regards to thickness, conformality, edge bead width and height.
- Work with Health and Safety department to identify unsafe practices and implement remedies.
-Train new technicians on correct process procedures.
•••••/••••• –•••••/•••••
DEVICE TECHNICIAN
Innovalight
Sunnyvale, CA
-Work with engineers to increase solar conversion efficiency.
-SEM cross sections of Silicon ink to evaluate grain size and densification quality.
-Train/mentor users on SEM / interface with vendor for SEM issues.
-Prepare/clean substrates for use in experiments.
-Print substrates with silicon ink/densify.
-Work with Health and Safety department to train technicians / monitor safety training schedules.
-Member of the HazMat team.
•••••/••••• –•••••/••••• Present
PROCESS TECHNICIAN
Fastec Technical Services supporting
Nanosys, Inc., Palo Alto, CA
-Work with engineers to optimize nano-wire growth, size, uniformity, and orientation.
-Prepare substrates for gold wire growth.
-Run particle count monitors and chart results to verify cleanroom cleanliness. Work with facilities to determine cause of high particles and resolve.
-Using a Field Emission Scanning Electron Microscope (FESEM), inspect gold spheres (pre-growth) and as-grown wires (post-growth).
-Use appropriate software to analyze gold sphere distribution and wire length distribution.
-Support wire “release” by using RIE and alcohol soak.
•••••/••••• •••••/•••••
START-UP ENGINEER - SACVD Demonstration Lab
Applied Materials, Santa Clara, CA
-Optimized dielectric films (O3/TEOS, Plasma Enhanced TEOS, mixed frequency TEOS) according to customer specifications and ran demos on AMAT P••••• and Centura
mainframes.
-Ran daily system checks to verify systems were operational.
-Interfaced/worked with maintenance personnel to troubleshoot/resolve system
problems.
-Interfaced with vendors when new equipment was brought into lab.
•••••/••••• •••••/•••••
Field Support – Start-Up Engineer SACVD
Applied Materials, Santa Clara, CA
-Performed Tier II (process) start-ups on SACVD Centura/P••••• systems at customer
sites.
-Supplied phone support to local account teams to aid in recovery of down equipment.
-Flew to customer sites to manage customer downs when local account team was unable
to resolve process/hardware problems.
-Collaborated with fellow engineers to write/amend process specifications and training manuals.
•••••/••••• •••••/•••••
PROCESS TECHNICIAN
Applied Materials, Santa Clara, CA
-Optimized processes according to customer specifications and ran demo wafers.
-Worked with engineering/maintenance to optimize hardware to improve process results.
-Maintained wafer inventory.
-Used various metrology equipment to analyze CVD and etch processes.
-Worked with outside vendors to install and characterize metrology equipment.
•••••/••••• •••••/•••••
WAFER FAB OPERATOR/ENGINEERING TECHNICIAN/ASSOCIATE ENGINEER. Siliconix Inc.(purchased by Vishay), Santa Clara, CA
-Dye Prep
-Masking
-Quality Control
-Pilot Line Technician
-Engineering Technician in R&D Group
-Associate Engineer in R&D Group
EQUIPMENT
EXPERIENCE
-AMAT Centura / AMAT P•••••
-Etch
-PECVD
-SACVD
-AMAT Endura
-SACVD
-PECVD
-Hitachi SEM
-Joel LVSEM – LV •••••
-Joel FESEM – JSM •••••F
-Nanometrics Measurements Tools
-Profilometer
-Rigaku XRF
-Particle monitor
-Oxidation/Diffusion Furnaces and ovens
-Resist spin coaters
-Surfscan Measurement Systems
-Wet Bench (acids and solvents)
-MS Windows, Word, Excel
-Image Pro Plus
-Familiarity with Auto Cad, Solidworks and ProE
PATENTS AND AWARDS
•••••/••••• US Patent# 6,•••••,•••••, Co-inventor
Apparatus for creating strong interface between in-situ SACVD and PECVD silicon
•••••/••••• US Patent# 5,•••••,•••••, Co-inventor
Method and apparatus for creating strong interface between in-situ SACVD and PECVD
silicon oxide films.
•••••/••••• Employee of the Quarter
Three Times Applied Material Employee of the Quarter
EDUCATION
•••••/••••• - •••••/••••• DeAnza Community College
-Engineering Drafting
-Introduction to and Intermediate Computer-Aided Design with Pro/ENGINEER
-Introduction to Computer-Aided Design with SolidWorks
•••••/••••• - •••••/••••• Mission College
-General Education
•••••/••••• - •••••/••••• Newark High School
REFERENCES
Available upon Request
