Physical Design Engineer

Michael A. •••••

BACKGROUND SUMMARY
••••• years of electronic hardware physical design implementation and verification experience. Expertise in SoC IC as well as hardware systems implementation. Expertise in physical verification. Expertise in EDA software architecture process, technical documentation and training. Expertise in analyzing current state of technology and balancing the tactical and strategic needs of an organization of either EDA or HW design companies. Excellent inter-departmental communications skills and ability to build consensus, define priorities and schedules, and allocate and manage resources.

TECHNICAL SKILLS
Recent EDA tools: ICC, Olympus-SoC, Magma Talus, Atoptech, Apache, Primetime, Celtic, Various Extractors
System tools: UNIX, shell, Tcl, LSF, Clearcase, Bugzilla
Documentation tools: Project, FrameMaker, Word, PowerPoint, Excel

PROFESSIONAL EXPEXRIENCE

IDT: Consulting Physical Designer. 1/••••• Present Responsible for
Full chip and block level physical implementation in Magma Fusion, including timing closure.
Toshiba TAEC: Consulting Physical Designer. 6/••••• •••••/••••• Responsible for:
Sign-off timing closure flow development, integrating Primetime and Talus optimizations of a hierarchical SoC design.
Samsung SSI: Senior Physical Design Engineer. 3/••••• 5/••••• Responsible for:
IC flow implementation and support for high speed, and low power high volume designs.
Mentor Graphic: Senior Technical Marketing Engineer. 5/••••• 3/••••• Responsible for:
Liaison between the field and R&D in the areas of Timing, Extraction, SI and Optimization.
Wrote many specifications for all areas of physical design.
Wrote training material including labs and presentations and User Guide.
Triaged bugs and enhancements from the field.
RMI Electronics: Staff Engineer. 5/••••• 5/••••• Responsible for:
Top level design implementation and flow development in Atoptech, including very coarse grain power gating flow for low power graphics processor design
Full chip timing verification in Primetime
Full chip Noise and crosstalk analysis in Celtic
Full chip power analysis in Apache
Interfaced with EDA vendors on daily basis to create hierarchical top level flow and develop automation features.
Interfaced with package and PCB designers as well as design architects and block level physical designers to top optimize floorplan.
Fastrack Design: Director of Engineer. •••••/••••• 5/••••• Responsible for:
Establishing TSMC •••••nM technology sign-off turnkey timing verification flow
Correlating the results of Fire&IceQX, Primetime, and Celtic with Magmas extraction, signal integrity analysis, timing analysis and delay calculation.
Running verification flow on all blocks and full chip and devise timing and noise ECOs.
Point man with foundry working to develop an ASIC model physical design flow. Established the necessary components for PD flow, documentation and training.
Personally implemented single chip digital/analog wireless communications device which had very low power requirements and included an on chip power regulator with multiple power domains, from RTL2GDS.



Michael A. •••••
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Airgo Networks: Physical Design Manager. •••••/••••• - •••••/••••• - Responsible for:
Architecting and running the physical design environment for SoC class physical designs.
Implemented all full chips and block level floor plans and power plans, and placed and routed seven •••••u SoC class designs targeted at mobile consumer markets. Resulting designs had utilizations between •••••% and •••••%, and manufacturing yields in the mid •••••s.
Implemented Magma physical design flow and Apache power analysis flows from scratch.
Architected physical verification flows including point tool verification using Sequence and Primetime.
Hiring 2 senior physical design engineers on to my team, and directing their efforts.
Managed strategic requirements of the company WRT physical design ramifications on cost and time to market.

Magma Design Automation: Product Engineer. 6/••••• •••••/•••••
- Responsible for:
Specification and schedules for clock and logic optimization product development.
Prioritize new features by interacting with customers, field engineers, marketing and R&D.
Define schedules by working with senior management and developers.
Researched and authored tactical and strategic documentation.
Developed training material and presented training sessions to all Magma engineers.
Technical Marketing Manager - Responsible for the specification delay calculation, SIA, STA.
Technical liaison between Magmas customers and R&D.
Developed strategies for improved delay calculation capabilities, and documented delay calculation processes.
Implemented and analyzed technical feasibility study of dynamic libraries used in design flow.
Published an article on tool integration, and its impact on design implementation processes.

Creative Technology: COT Tools Flow Architect. •••••/••••• 6/••••• Responsible for:
Physical implementation and verification methodologies.
Identify the best available technology to insure both time to market and reliability of the product.
Decrease component costs by •••••% of an audio product high volume design.
Tape-out timing verification flow development of high-end graphics processor design.

Sun Microsystems Computer Corporation: Senior CAD Tools Engineer. •••••/••••• •••••/••••• - Responsible for:
Researching and implementation of STA methodologies needed for DSM standard cell design sign-off verification.
Designed and implemented multi-ASIC vendor STA flows which were utilized corporate wide.
Designed augmentation to ASIC vendor flows that automated timing driven in place optimization (IPO).
Utilized STA and IPO flows on all ASICs used in the desktop product.

Network Equipment Technology: Principal CAE Engineer. 1/••••• •••••/••••• - Responsible for:
Design and implementation of an automated flow to physically implement and verify a large scale ATM switch. This switch consisted of multiple ••••• layer PCBs, over ••••• ICs including ••••• FPGAs, ••••• ASICs, ••••• VLSI chips, and ••••• memory subsystems.
Automated flow by integrating STA and SIA with the FPGA and ASIC flows, along with the PCB place and route. This design powered up in three weeks, when originally estimated at three months. First pass manufacturing yields were above •••••%.
Substantially reduced manufacturing costs by reusing automated R&D implementation flow to verify second source parts.
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AVID/Digidesign: CAE Manager. •••••/••••• 1/••••• - Responsible for:
Establishing FPGA, ASIC and PCB physical implementation and verification flows, along with quality standards and user documentation.
Enabled multi-site design collaboration between AVID and Digidesign design teams by building consensus on flow features and schedules for implementation.

QUAD Design Technology: Senior CAE Engineer. •••••/••••• •••••/••••• - Responsible for:
PCB and ASIC analysis product development and MOTIVE STA training.
On-site consulting and training with customers to facilitate implementation of STA use model.

Pyramid Technology Corporation: Developer and manufacture UNIX computers. •••••/••••• •••••/•••••
CAE Engineer (H/W R&D) - Responsible for:
Physical verification of ASICs and PCBs, and CAD tools support.
Developed, integrated, and supported flows utilized by design teams consisting of MOTIVE STA for ASIC and PCB design with, XTK SIA flows for PCB design.
Improved first pass yields and product reliability by implemented a redesign of a system support processor PCB, based on STA and SIA flow.
Increased manufacturing yields from •••••% to •••••% by introducing a formalized use of STA and SIA in the R&D design flow.
Project Support Engineer (H/W R&D) - Responsible fo:
Communications with Marketing, Engineering, Manufacturing and Field Service to address technology and schedule issues on new systems configurations and system components.
Projects ranged from large scale systems integration to new I/O and CPU releases.
Technical Analyst (Manufacturing Engineering) - Responsible for:
Automating, implementing, and documenting the Production Change Request process.
Increased first pass manufacturing yields •••••% by developing and implementing a Closed Loop Corrective Action process.
Lead Test Technician (Manufacturing) - Responsible for:
Direct supervision of ••••• system and component level test technicians.
Recorded, tacked and reported all manufacturing board failures by developing and implemented a board failure statistical analysis database.
Senior Test Technician (Manufacturing) - Responsible for:
Troubleshooting all I/O and CPU PCBs from the system to component level.

Manufacturing and Field Technician at various computer and robotics companies:
BTI Computer Systems: Developer and manufacture of large scale compute servers. 7/••••• •••••/•••••
TAK Automation, Inc.: Developed and manufacture robotic crane control systems. 7/••••• - 7/•••••
Four Phase Corporation: Developer and manufacture of large-scale computer systems. •••••/••••• 7/•••••
Responsible for:
System to component level troubleshooting of all components in computer systems done to the component level.

EDUCATION: AS Electrical Engineering, ITT Technical Institute, Portland Oregon •••••